1. Field of the Invention
The present invention relates to an inverter circuit for generating a clock signal and the like.
2. Description of the Related Art
A reduction in power consumption is required for an LSI (Large Scale Integration) mounted on battery-operated equipment represented by mobile devices. 20% to 45% of electric power consumed within the LSI is consumed as power for the charging and discharging of capacitances by clock signals. Thus, the reduction in power consumed by the charging and discharging will be effective in the reduction of power consumption of LSI.
The power consumed by the charging and discharging by the clock signals is proportional to the square of power supply voltage. Thus, in order to reduce the power consumed by the switching of the clock signal, a method for reducing the amplitude of clock signal has been proposed.
As shown in FIG. 1, a diode 13 is inserted between a P-channel MOS transistor 1 and an output signal line 12, whereas a diode 14 is inserted between an N-channel MOS transistor and the output signal line 12, thereby adjusting the potential of the output signal line 12 to a low amplitude.
In the above-described circuit, the amplitude level of the output signal is dependent on a forward voltage Vf of the diode. The forward voltage Vf of the diode is determined by a work function difference. Thus, it is difficult to adjust the amplitude level to an arbitrary potential. Also, when the power supply voltage is a low voltage, which is lower than approximately 1.8 V, for instance, it is also difficult to generate from a given voltage a potential lower than the given voltage.